The present invention relates to a stack package, and more particularly, to a through-silicon via stack package that is lightweight and compact and that forms excellent electrical connections, and a method for manufacturing the same.
Previous developments in packaging technology for semiconductor integrated circuits have been driven by the demands of miniaturization and high capacity. In the prior art various techniques for stack packages that provide satisfactory results in terms of miniaturization, high capacity, and mounting efficiency have been developed.
The term “stack”, as referred to in the semiconductor industry, means to vertically pile at least two chips or packages. In memory devices by stacking chips or packages it is possible to realize a product having a memory capacity that is greater than what is obtainable through semiconductor integration processes, and also by stacking the chips or packages mounting area utilization efficiency can be improved.
Stack package manufacturing methods can be divided into a first method in which individual semiconductor chips are stacked and the stacked semiconductor chips are packaged, and a second method in which individually packaged semiconductor chips are stacked upon one another. In a typical stack package, electrical connections are formed by metal wires or through-silicon vias.
FIG. 1 is cross-sectional view illustrating a conventional stack package using metal wires.
Referring to FIG. 1, in the conventional stack package 100 using metal wires, at least two semiconductor chips 110 are stacked on a substrate 120 by the medium of adhesive 114, and the respective chips 110 and the substrate 120 are electrically connected to each other by metal wires 116.
In FIG. 1, the unexplained reference numeral 112 designates bonding pads, 122 connection pads, 124 ball lands, 170 outside connection terminals, and 190 an encapsulant.
However, in the conventional stack package 100 using metal wires, electrical signal exchange is conducted through the metal wires 116, which causes a slow operation speed in each semiconductor chip 110. Also, the metal wires 116 cause the electrical characteristics of each chip 110 to be degraded. Further, an additional area for accommodating the metal wires 116 is needed in the substrate 120, thus increasing the size of the stack package 100, and a gap is needed to bond the metal wires 116 to the respective chips 110, thus increasing the overall height of the stack package 100.
In order to overcome the problems caused in by a stack package using metal wires, (i.e. prevent the electrical characteristics of the stack package from being degraded, and enable the stack package to be miniaturized), a stack package using through-silicon vias (TSVs) has been suggested in the art.
FIG. 2 is cross-sectional view illustrating another conventional stack package using through-silicon vias.
Referring to FIG. 2, in a conventional stack package 200 using through-silicon vias, semiconductor chips 210 having through-silicon vias 230 formed therein are stacked on a substrate 220 in a manner such that the through-silicon vias 230 of the chips 210 face each other.
In FIG. 2, the unexplained reference numeral 212 designates an insulation layer, 214 a metal seed layer, 222 connection pads, 224 ball lands, 270 outside connection terminals, and 218 metal lines.
In the stack package 200 using through-silicon vias, by forming the electrical connections using through-silicon vias 230, it is possible to prevent the electrical characteristics of each chip 210 from being degraded. Therefore, the operation speed of the semiconductor chip 210 can be increased, and the semiconductor chip 210 can be miniaturized.
However, in the conventional stack package 200 using through-silicon vias, because of the small surface area of the portions of the through-silicon vias 230 which project out of the semiconductor chips, when electrically connecting the stacked semiconductor chips 210 to one another it is difficult to precisely align the through-silicon vias 230. Moreover, the projecting portion of the through-silicon vias 230 and the metal lines 218 which the projecting portion is connected to cause the thickness of the stack package 200 to increase.